1 bit full adder

We found following good implementations to compare:


1. Gate-level netlist designed by AMD XILINX VIVADO design tool. Power: 246, area: 440, 84 ps carry look-ahead delay, 108 ps maximum delay, max. levels: 3, max gate fan-out: 1, max input fan-out: 3, 7 gates, 62 transistors, 16 wires
Source: Full adder design and simulation in AMD XILINX Vivado Tool


2. Power, 182, area: 340, 133 ps carry look-ahead delay, 133 ps maximum delay, 3 levels, 5 gates, 50 transistors, 12 wires
Source: cadec-2019-VIT-AP

Our results

We used this gate setting.

Here is our Truth Table.

Here are all our 71 results.

Version 1. Fast carry look-ahead version:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

This our version of 1 bit full adder circuit outperforms the AMD XILINX Vivado version in several key areas:

• it reduces power consumption by 1.52 times,
• improves delay (performance) by 1.78 times,
• decreases area requirements by 1.32 times,
• cuts gate count by 1.16 times,
• reduces transistor count by 1.24 times,
• and lowers wire usage by 1.06 times.

Version 2. Minimum area and power:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Version 3. Fastest version:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic: