New Challenges for the FPGA Logic Synthesis Stage
(ALU Control Unit)

As modern FPGAs continue to scale, wire area and delay are becoming more dominant than logic-related delays. Wire quantity and length all contribute to wire area.

Additionally, larger LUTs (with more inputs) result in higher delay, increased area usage, and greater power consumption. Reducing the number of LUT inputs by just one can lower area and power usage by more than 2×. For example, a LUT-4 can be built from two LUT-3s connected by a 2:1 multiplexer.




High fan-out of circuit inputs, along with the need for buffering and replication, further worsens area and delay.


In the GTs synthesis technology, we addressed all these issues during the logic synthesis stage.

However, current evaluations of LUT-6 mapped benchmarks typically rely on only two parameters:

• the number of LUTs, and
  
• the number of logic levels.
  

We recommend adding the following parameters for a more complete evaluation:

• Total number of wires
  
• Number of input-connected wires
  
• Total number of LUT input pins used
  
• Maximum fan-out for circuit inputs and LUT outputs
  
  

Below is an example of how we improved the version "ctrl_size_2023" of the ALU Control Unit circuit to achieve the best result in the IPFL benchmark 2024

Original version "ctrl_size_2023" of the "ALU control unit" circuit in the best result IPFL benchmark 2024

This version has the following characteristics:

• LUT count: 25
  
• Logic level count: 2
  
• Total wire count: 148
  
• Input-connected wires count: 119
  
• Total LUT input pins used: 123
  
• Maximum input fan-out: 25
  
  

GTs version "ctrl_size_2025" of the "ALU control unit" circuit

This version "ctrl_size_2025" has the following characteristics:

• LUT count: 25
  
• Logic level count: 2
  
• Total wire count: 140
  
• Input-connected wires count: 90
  
• Total LUT input pins used: 115
  
• Maximum input fan-out: 19
  
  

It outperforms the original version "ctrl_size_2023" of the "ALU control unit" circuit from best result IPFL benchmark 2024 in following key areas:

• Reduces LUT area and power consumption by 1.13× (10%),
  
• Decreases wire area and power requirements minimum by 1.05× (5.4%),
  
• Cuts the circuit input buffer count from 15 to 10 (by 1.5×, 33.3% - max input fan-out from 25 to 19),
  
• Lowers the usage of input-connected (longest) wires by 1.32× (24.3%).