4 bit adder

We found two recent implementations to compare:


1. Power: 791, carry look-ahead delay: 169 ps , maximum delay: 220 ps , Area: 1600, max. levels: 6, 36 gates, 192 transistors, 76 wires, max. fan-out: 3 :



2. Power: 913, carry look-ahead delay: 247 ps , maximum delay: 273 ps , Area: 1737, 6 levels, 32 gates, 228 transistors, 72 wires, max fan-out: 6

Our results

We used this gate setting.

Here is our Truth Table.

Here are all our 910 results.

Version 1. Fast carry look-ahead version:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Version 2. Minimum area and pover:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic: