GT PDBF Logic Synthesis Benchmark Suite

Purpose of the benchmark suite

This page provides reproducible PDBF synthesis problems in standard PLA format. The benchmarks include semantic control and policy functions as well as dedicated input-scalability experiments extending to one million primary inputs.

GT synthesis results are reported as simple two-input logic-gate count, maximum logic depth, and synthesis time. The present benchmark release provides the original PLA specifications and synthesis statistics. GT synthesized netlists are not included in this release.

PDBF model. For an input cube x_i ∈ {0,1,−}ⁿ and output pattern y_i ∈ {0,1,−}^m, specified 0 and 1 values are mandatory over the complete input region represented by the cube, while “−” is a don't-care.

Availability of ABC comparison data

ABC results are shown only for benchmarks that we were able to process using ABC. The two comparison tables below therefore include ABC columns only where an ABC netlist/result was obtained.

The medium-input semantic benchmark table and the input-scalability table that follow intentionally contain GT results only: for those benchmark cases we did not obtain corresponding ABC synthesis results.

FSM / memory-oriented PDBF synthesis results

These benchmarks provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

Benchmark	PI	PO	Cubes	ABC		GT		PLA
Benchmark	PI	PO	Cubes	Gates	Levels	Gates	Levels	PLA
`axi_lite_slave_transaction_fsm_semantic.`	17	20	32	78	12	71	13	PLA
						75	11
						81	10
						87	9
						104	8
						118	7
`can_receive_filter_fsm_semantic`	16	20	91	113	11	97	20	PLA
						99	16
						100	12
						138	11
						144	10
						145	9
						150	8
`ethernet_frame_classifier_fsm_semantic`	17	20	29	92	9	82	18	PLA
						85	15
						86	14
						88	12
						91	11
						93	10
						124	9
						125	8
						131	7
`i2c_target_transaction_fsm_semantic`	16	19	42	116	12	106	33	PLA
						109	13
						136	12
						142	9
`ipv4_ipv6_acl_packet_classifier_semantic`	512	12	4,096	134,536	59	509	64	PLA
						537	59
						542	52
						564	49
						577	47
						609	46
						630	41
						641	38
						647	33
`nvme_submission_queue_command_fsm_semantic`	20	20	198	125	12	95	23	PLA
						98	20
						99	19
						100	17
						101	14
						111	13
						126	10
						127	9
`pcie_tlp_transaction_header_fsm_semantic`	20	21	120	129	11	86	14	PLA
						88	11
						90	10
						91	9
						92	8
						119	7
`riscv_pipeline_hazard_forwarding_semantic`	22	18	101	52	7	35	13	PLA
						37	12
						38	8
						44	7
`riscv_privileged_trap_csr_controller_semantic`	34	24	177	114	13	69	15	PLA
						70	13
						75	12
						92	11
						108	8
						119	7
`sdcard_spi_command_fsm_semantic`	17	20	79	131	17	114	23	PLA
						115	22
						117	19
						118	18
						121	15
						125	14
						161	11
						165	10
						179	9
`spi_transaction_fsm_semantic`	16	19	45	115	17	103	24	PLA
						109	23
						110	19
						112	15
						125	11
						161	10
						166	9
						177	8
`uart_rx_fsm_semantic`	8	10	26	35	12	32	7	PLA
						34	6
						35	5
`usb_control_transfer_fsm_semantic`	17	21	43	109	15	113	19	PLA
						119	16
						121	14
						127	13
						178	11
						182	10
						183	9
						199	8

The first line of each benchmark section identifies the benchmark and gives PI, PO, Cubes, the available ABC result, the first GT result, and the PLA download link. Additional lines show alternative GT netlist variants for the same PDBF.

Semantic PDBF synthesis results with available ABC comparisons

These semantic benchmarks provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

Benchmark	PI	PO	Cubes	ABC		GT		PLA
Benchmark	PI	PO	Cubes	Gates	Levels	Gates	Levels	PLA
`axi_transaction_response_error_policy_semantic`	26	20	3,152	95	5	78	23	PLA
						79	13
						80	11
						84	10
						91	9
`can_11bit_identifier_decoder_native`	11	8	33	48	6	12	4	PLA
						13	3
`CAN_CANFD_frame_control_decoder`	8	11	128	26	5	21	6	PLA
						22	4
`CV32E40P_v1.0_actual_decoder_control_projection`	32	23	69	127	19	43	6	PLA
						57	4
						48	5
`DALI_command_decoder`	9	4	83	56	7	7	5	PLA
						11	4
`DMX512_start_code_decoder`	8	4	4	18	4	2	1	PLA
						2	1
`ethernet_mac_address_filter_native`	48	4	16	112	8	2	1	PLA
						2	1
`FlexRay_header_semantic_decoder`	16	5	132	21	7	2	2	PLA
						2	2
`i2c_target_register_control_semantic`	10	14	16	41	8	24	4	PLA
`Ibex_RV32IM_actual_control_projection`	32	22	58	116	12	51	9	PLA
						52	7
						56	6
						66	5
`LIN_protected_identifier_decoder`	8	8	62	34	11	3	2	PLA
						3	2
`mdio_clause22_semantic_controller`	12	13	15	31	7	17	4	PLA
						19	3
`Modbus_public_function_decoder`	8	7	19	39	6	24	7	PLA
						26	5
`pcie_axil_master_minimal_source`	27	37	18,432	90	11	66	7	PLA
						68	5
`pcie_bar_address_routing_controller_semantic`	27	20	998	109	16	69	15	PLA
						71	12
						77	11
`pcie_completion_validation_error_policy_semantic`	26	20	1,328	98	15	75	14	PLA
						77	13
						81	12
						83	11
						87	10
`PicoRV32_default_actual_decode_projection`	32	39	40	98	6	62	4	PLA
						67	3
`SERV_MDU_actual_serv_decode_projection`	14	48	3,565	135	15	56	8	PLA
						66	5
`spi_semantic_command_register_controller`	9	15	15	47	8	22	3	PLA
`usb_cdc_setup_source_derived`	64	36	30,720	201	13	80	19	PLA
						82	17
						83	12
						84	11
						112	10
`usb_hid_setup_semantic_controller`	64	25	33	242	20	36	6	PLA
						37	5
						41	3
`VexRiscv_GenSmallest_plugin_decode_projection`	32	12	49	89	10	19	4	PLA
						20	3

Medium-input semantic PDBF benchmarks

In this benchmark suite, examples with hundreds to several thousand primary inputs are classified as medium-input PDBFs. The cases below model networking, security, storage, telecommunications and policy/control hardware.

Benchmark	PI	PO	Cubes	GT Gates	GT Levels	GT Time, s	PLA
`ipv4_ipv6_acl_packet_classifier_semantic`	512	12	4,096	647	33	151	PLA
`ipv6_5g_upf_gtpu_policy_semantic`	1,344	18	16,384	273	43	43	PLA
`ipv6_bgp_evpn_route_policy_semantic`	1,312	18	16,384	14	3	0.5	PLA
`ipv6_dns_doh_security_policy_semantic`	1,296	18	16,384	682	98	142	PLA
`ipv6_firewall_policy_classifier_semantic`	806	14	8,192	4,147	223	2,142	PLA
`ipv6_geneve_nsh_service_chain_policy_semantic`	1,392	17	16,384	2,979	162	2,044	PLA
`ipv6_ids_ips_signature_policy_semantic`	1,248	18	16,384	3,257	164	9,365	PLA
`ipv6_ipsec_sa_security_policy_semantic`	1,280	18	16,384	3,488	167	7,161	PLA
`ipv6_macsec_zero_trust_policy_semantic`	1,328	17	16,384	5,794	238	12,109	PLA
`ipv6_mpls_srv6_interworking_policy_semantic`	1,368	18	16,384	3,843	202	4,157	PLA
`ipv6_nvmeof_storage_policy_semantic`	1,360	18	16,384	1,909	147	1,013	PLA
`ipv6_ptp_tsn_policy_semantic`	1,280	18	16,384	1,890	141	1,008	PLA
`ipv6_quic_ddos_mitigation_policy_semantic`	1,152	18	16,384	823	67	196	PLA
`ipv6_quic_tls_sase_policy_semantic`	1,304	17	16,384	3,776	204	4,393	PLA
`ipv6_rocev2_rdma_congestion_policy_semantic`	1,320	18	16,384	2,919	198	2,395	PLA
`ipv6_security_telemetry_policy_medium_semantic`	1,000	16	8,192	290	47	31	PLA
`ipv6_service_chain_security_policy_narrow_semantic`	946	16	8,192	1,527	134	756	PLA
`ipv6_service_mesh_load_balancer_policy_semantic`	1,216	18	16,384	3,484	208	3,424	PLA
`ipv6_srv6_service_policy_classifier_semantic`	1,408	18	16,384	3,283	200	6,185	PLA
`ipv6_storage_replication_erasure_policy_semantic`	1,376	17	16,384	3,552	217	4,073	PLA
`ipv6_vxlan_microsegmentation_ct_policy_semantic`	1,024	18	12,288	1,420	135	337	PLA

The PLA files should be uploaded using exactly the benchmark filenames shown in the first column.

Randomly generated PDBFs: cube quantity to netlist parameters comparison

This experiment keeps the benchmark size fixed at 250 primary inputs and 1 primary output while increasing the number of PDBF cubes from 16 to 2,000. The table compares the resulting ABC and GT netlist gate counts and logic levels.

Benchmark	PI	PO	Cubes	ABC		GT		PLA
Benchmark	PI	PO	Cubes	Gates	Levels	Gates	Levels	PLA
`E250_1_16`	250	1	16	708	16	1	1	PLA
`E250_1_32`	250	1	32	2,175	30	4	3	PLA
`E250_1_64`	250	1	64	3,783	35	9	5	PLA
`E250_1_128`	250	1	128	7,003	35	21	6	PLA
`E250_1_256`	250	1	256	13,648	37	45	8	PLA
`E250_1_500`	250	1	500	25,779	42	95	14	PLA
`E250_1_1000`	250	1	1,000	46,256	44	209	20	PLA
`E250_1_2000`	250	1	2,000	82,107	44	431	28	PLA

Each PLA button links to /benchmarks/<Benchmark>.pla.

PDBF input-scalability challenge

This separate series studies synthesis as the primary-input dimension grows from hundreds to tens of thousands, hundreds of thousands and one million inputs.

Benchmark	PI	PO	Cubes	GT Gates	GT Levels	GT Time, s	PLA
`Example_250_1_2000`	250	1	2,000	431	28	4	PLA
`Example_250_100_2000`	250	100	2,000	38,272	78	1,063	PLA
`Example_10000_1000_5000`	10,000	1,000	5,000	769,799	47	26,875	PLA
`Ex100000_1_1000`	100,000	1	1,000	89	15	63	PLA
`Ex_1000000_1_100`	1,000,000	1	100	6	4	4	PLA

The results illustrate that primary-input count alone does not determine synthesis difficulty. The care structure, number of outputs, cube structure and interactions among conditions can be equally important.

Reported synthesis metrics

PI — number of primary inputs. PO — number of primary outputs. Cubes — number of PLA product terms.

For the GT results, Gates denotes the number of internal two-input simple/AIG logic nodes. Complemented AIG edges do not count as additional gates. Levels is the maximum logic depth from a primary input to a primary output.

GT Time is the reported synthesis runtime in seconds for the corresponding experiment.

Verification rules and acceptance criteria

A synthesized network is a valid implementation of a benchmark only if it satisfies every specified PDBF output value over the complete care domain of the PLA.

For every PLA cube and every output specified as 0, the synthesized output must be 0 for every concrete binary input assignment covered by that cube.
For every PLA cube and every output specified as 1, the synthesized output must be 1 for every concrete binary input assignment covered by that cube.
An output value - is unrestricted. A term for which all outputs are - imposes no PDBF constraint and should not be included in the effective truth table.
Verification must cover the complete input region represented by a cube, not only one representative minterm. If a PLA input is - and belongs to the effective support of the synthesized output, all relevant assignments of that free support variable must be checked or proven equivalent.
If all primary inputs in the effective support of an output are fixed within a PLA cube, evaluation of that support assignment proves the output over the complete cube; primary inputs outside the output support cannot affect the result.
Two overlapping cubes may not impose contradictory values on the same output. If two terms require opposite values, 0/1 or 1/0, for an output, their input cubes must be disjoint. Therefore at least one input position must contain an explicit complementary pair 0/1 or 1/0.
Behavior outside the PDBF care domain is unrestricted. Two valid synthesized networks do not have to be globally equivalent if they make different choices in don't-care regions.

Verification status: a result should be described as VERIFIED only when the complete PDBF care domain has been checked or proven against the synthesized network. Simulation of selected test vectors alone should be described as sampled or unverified.

Results obtained with other synthesis tools

We welcome independent experiments with these benchmarks. If you obtain a synthesis result using another combinational logic synthesis tool, please inform us of the result and the synthesis conditions.

For meaningful comparison, please identify the tool and version, synthesis commands/options, hardware platform, runtime, peak memory if available, gate/node count and logic depth. The resulting implementation can be validated against the original PLA using the verification criteria above.

A valid result with fewer gates, fewer levels, or competitive synthesis time is welcome.

Input-size terminology used in this suite

The terms below are benchmark-suite classifications rather than claims of universal EDA terminology:

Class	Primary inputs
Small	< 250
Medium	250 – 9,999
Large	10,000 – 99,999
Very large	100,000 – 999,999
Extreme	≥ 1,000,000