Abstract
Many digital control functions are naturally specified only over a subset of their Boolean input space. Processor decoders operate on meaningful instruction encodings, protocol controllers respond to legal transactions, register interfaces distinguish implemented from reserved addresses, and communication devices process only semantically valid combinations of command, state, and data fields. Outside these domains, circuit behavior may be irrelevant to the intended functionality.
Conventional logic synthesis, however, is commonly applied to a Boolean network representing a particular realization of the specification. This paper investigates an alternative formulation, termed Design from Semantics (DfS), in which synthesis operates directly under the compatibility constraints of a partially defined Boolean function (PDBF). Given a care domain D and required behavior F:D→{0,1}m, a candidate circuit C is considered correct when
while its behavior outside D remains unconstrained. This formulation permits synthesis to exploit semantic incompleteness directly during implementation search rather than requiring preservation of a particular behavior over the entire Boolean input space.
The approach is evaluated on processor-control projections and protocol-oriented semantic controllers, including RISC-V decode/control functions, CAN, Ethernet, DALI, DMX512, FlexRay, LIN, Modbus, PCIe/AXI-Lite, USB CDC, SPI, I²C, MDIO, and USB HID examples. Implementations obtained by direct semantic synthesis are compared with those produced by an evaluated conventional ABC synthesis flow using gate count, maximum logic depth, wire count, maximum gate fan-out, and maximum primary-input fan-out.
Substantial structural differences are observed across the benchmark set. For example, an SPI semantic controller is reduced from 47 gates and 8 levels to 22 gates and 3 levels, while a USB HID semantic controller is reduced from 242 gates and 20 levels to 36 gates and 6 levels. Alternative semantic implementations expose additional area-depth trade-offs.
The results show that direct synthesis under care-domain compatibility can discover implementations substantially different from—and, in these experiments, often smaller and shallower than—those obtained by the evaluated conventional synthesis flow. These observations suggest that semantic incompleteness can be treated as an optimization resource rather than merely as a property of the specification.
1. Introduction
Logic synthesis is traditionally concerned with transforming a Boolean representation into a structurally improved implementation while preserving its required functionality. Typical objectives include reductions in circuit area, logic depth, interconnection complexity, power, or combinations of these quantities.
For a completely defined Boolean function F:{0,1}n→{0,1}m, correctness requires a synthesized circuit C to satisfy C(x)=F(x) for every input assignment. This formulation is natural when every possible input combination has a required interpretation.
Many control-oriented digital systems, however, do not naturally possess such a complete specification. A processor decoder is required to respond correctly to meaningful instruction encodings. A communication controller processes commands that are legal under the protocol. A register interface recognizes implemented addresses and supported operations. A USB request controller responds to supported combinations of request type, request code, value, index, and length. Large portions of the mathematical Boolean input space may therefore have no required system-level meaning.
Such functions are naturally modeled as partially defined Boolean functions. Let D⊆{0,1}n be the semantic care domain, and let F:D→{0,1}m describe the required behavior. An implementation is correct if
Behavior for x ∉ D is not required by the semantic specification.
The distinction changes the synthesis objective from preserving one completely defined Boolean function to searching the set of all circuits compatible with a semantic relation. This paper investigates this alternative synthesis viewpoint, which we call Design from Semantics (DfS).
The objective is not to argue that conventional synthesis systems are incorrect when processing incompletely specified functions. Instead, we investigate whether searching directly under care-domain compatibility can expose implementations that differ structurally from those obtained by the evaluated conventional synthesis flow.
The principal result is that direct synthesis under care-domain compatibility can discover implementations substantially different from—and, in the evaluated benchmarks, often smaller and shallower than—those obtained by the evaluated conventional synthesis flow.
2. Semantic Care Domains
2.1 Completely Defined Boolean Functions
For a completely defined function, the implementation requirement is global. Two implementations are equivalent only when their outputs agree for every possible input assignment.
2.2 Partially Defined Boolean Functions
A PDBF specifies F:D→Bm, where B={0,1} and D⊆Bn. Only assignments belonging to D constrain implementation behavior. The complement D̄=Bn\D contains assignments whose outputs are semantically unspecified.
Consequently, two circuits may differ for inputs outside D and nevertheless both be correct implementations if they agree with F for every care assignment. We call this relation care-domain compatibility.
3. Semantic Incompleteness as an Optimization Resource
A partially defined specification implicitly represents a family of possible complete Boolean functions. Every member agrees with the required semantics on D but may assign different values outside the care domain. These completions need not have equal implementation complexity.
Crucially, no constraint is imposed for x∉D. This freedom is not artificial in many applications. It arises from system semantics: reserved instruction encodings, unsupported protocol commands, unimplemented registers, unmatched device addresses, unreachable states, illegal transactions, reserved request types, and field combinations that cannot arise during valid system operation.
DfS treats this semantic incompleteness as part of the optimization space.
4. Design from Semantics
A conventional synthesis process can be viewed conceptually as the sequence above. DfS emphasizes a different route:
The distinction does not imply that conventional optimization cannot exploit don't-care information. Rather, it concerns where the synthesis search is formulated and which equivalence relation constrains candidate implementations. In DfS, candidate circuits need not be globally equivalent to one predetermined complete Boolean function. They need only belong to the compatibility class defined by D.
4.1 Multi-Objective Implementation Cost
In this study, an implementation is characterized by the vector
where G is gate count, L is maximum logic depth, W is wire count, FG is maximum gate fan-out, and FI is maximum primary-input fan-out. Semantic synthesis may therefore generate multiple useful solutions rather than one uniquely optimal network.
5. Experimental Methodology
The experimental set contains several families of control-oriented Boolean functions.
- Processor-control functions: CV32E40P, Ibex RV32IM, PicoRV32, and VexRiscv decode/control projections.
- Communication and control functions: CAN, CAN/CAN-FD, Ethernet MAC filtering, DALI, DMX512, FlexRay, LIN, Modbus, PCIe/AXI-Lite, and USB CDC.
- Semantic protocol controllers: SPI command/register control, I²C target/register control, MDIO Clause-22 management, and USB HID SETUP-request control.
The latter group explicitly retains combinations that are semantically unspecified.
6. Reference Synthesis and Comparison
ABC is used as the conventional synthesis reference. The purpose of this comparison is not to characterize ABC as incorrect. Instead, ABC provides a mature conventional synthesis flow against which the structural consequences of direct semantic synthesis can be examined.
When different optimization sequences produce different non-dominated area/depth results, multiple solutions are retained. The same principle is applied to GT results. For example, MDIO produces the verified GT alternatives 17 gates / 4 levels / 47 wires and 19 gates / 3 levels / 51 wires.
7. Independent Correctness Verification
Structural optimization is meaningful only after semantic correctness has been established. For every candidate network considered for inclusion in the experimental results, the implementation is independently evaluated over all enumerated care assignments and compared against the PDBF specification.
A candidate that has lower gate count or depth but violates even one required care condition is rejected.
Semantic validity precedes structural quality.
8. Experimental Results
8.1 Processor-Control Examples
The processor benchmarks demonstrate substantial structural differences. For CV32E40P, ABC produces 127 gates, 19 levels, and 272 wires. GT produces alternatives including 35/7/93 and 37/5/97. For Ibex RV32IM, the ABC result is 116/12/258, while GT obtains 41/5/104 and 48/4/118. For VexRiscv, ABC gives 89/10/190, while GT obtains 18/4/48 and 21/3/54. These results indicate that the observed behavior is not confined to protocol decoders.
9. Semantic Protocol Controllers
9.1 SPI Command/Register Controller
The SPI benchmark contains 9 inputs and 15 outputs. Its semantic cubes expand to 114 concrete care assignments. Two ABC solutions were observed: 47/8/109 and 43/12/101. The verified GT implementation contains 22/3/59.
Compared with the 47-gate ABC solution, gate count decreases by 53.2%, maximum depth decreases from 8 to 3 (62.5%), and wire count decreases from 109 to 59 (45.9%).
10. I²C Target/Register Controller
The I²C benchmark contains 10 inputs and 14 outputs. Its semantic specification expands to 98 care assignments out of 1,024 possible Boolean input combinations, giving a care density of approximately 9.57%. ABC produces 41/8/96 and 38/10/90. GT produces 24/5/62 and 25/4/64. Neither GT solution dominates the other; the first favors area and wiring, while the second trades one additional gate and two wires for reduced depth.
11. MDIO Clause-22 Semantic Controller
The MDIO benchmark contains 12 inputs and 13 outputs and has 52 concrete care assignments. The ABC alternatives are 31/7/75 and 30/9/73. The verified GT solutions are 17/4/47 and 19/3/51. The first reduces gates from 31 to 17 (45.2%) and wires from 75 to 47; the second provides a lower-depth operating point.
12. USB CDC Control
USB CDC provides a substantially larger semantic-control example with 64 primary inputs, 36 outputs, and a bounded care domain containing 30,720 specified input combinations. The ABC reference implementation contains 201/13/428. GT provides several structural alternatives: 80/19/196, 82/17/200, 83/12/202, 84/11/204, and 112/10/260. The benchmark is instructive because minimizing gate count alone does not minimize depth.
13. USB HID Semantic Controller
The USB HID benchmark uses the natural 64-bit USB SETUP request representation and 25 semantic outputs. The evaluated ABC implementation contains 242 gates, 20 levels, and 509 wires. GT discovers three useful implementations: 36/6/94, 37/5/99, and 42/4/109.
The minimum-gate solution reduces gate count by approximately 85.1% and wire count by approximately 81.5%. The depth-oriented 42-gate solution reduces maximum logic depth from 20 to 4, corresponding to an 80% reduction.
14. Selected Comparative Results
| Benchmark | Method | Gates | Levels | Wires | Max Gate F-O | Max Input F-O |
|---|---|---|---|---|---|---|
| CV32E40P | ABC | 127 | 19 | 272 | 7 | 7 |
| GT | 35 | 7 | 93 | 6 | 4 | |
| GT | 37 | 5 | 97 | 6 | 6 | |
| Ibex RV32IM | ABC | 116 | 12 | 258 | 6 | 8 |
| GT | 41 | 5 | 104 | 4 | 5 | |
| GT | 48 | 4 | 118 | 4 | 5 | |
| VexRiscv | ABC | 89 | 10 | 190 | 5 | 7 |
| GT | 18 | 4 | 48 | 4 | 3 | |
| GT | 21 | 3 | 54 | 3 | 5 | |
| SPI | ABC | 47 | 8 | 109 | 5 | 6 |
| ABC | 43 | 12 | 101 | 8 | 5 | |
| GT | 22 | 3 | 59 | 4 | 5 | |
| I²C | ABC | 41 | 8 | 96 | 4 | 8 |
| ABC | 38 | 10 | 90 | 5 | 6 | |
| GT | 24 | 5 | 62 | 4 | 5 | |
| GT | 25 | 4 | 64 | 4 | 4 | |
| MDIO | ABC | 31 | 7 | 75 | 4 | 5 |
| ABC | 30 | 9 | 73 | 5 | 5 | |
| GT | 17 | 4 | 47 | 4 | 3 | |
| GT | 19 | 3 | 51 | 4 | 3 | |
| USB CDC | ABC | 201 | 13 | 428 | 7 | 8 |
| GT | 80 | 19 | 196 | 5 | 4 | |
| GT | 84 | 11 | 204 | 6 | 6 | |
| GT | 112 | 10 | 260 | 6 | 5 | |
| USB HID | ABC | 242 | 20 | 509 | 6 | 12 |
| GT | 36 | 6 | 94 | 4 | 8 | |
| GT | 37 | 5 | 99 | 4 | 5 | |
| GT | 42 | 4 | 109 | 3 | 6 |
The complete experimental archive may contain additional benchmarks and alternative implementation points; this page highlights the principal comparisons used in the paper narrative.
15. Discussion
15.1 RQ1 — Implementation Complexity
The experimental evidence indicates that direct care-domain synthesis can reduce implementation complexity. Substantial gate reductions are observed across multiple benchmark families, often accompanied by reductions in depth and wiring.
15.2 RQ2 — Different Control Semantics
The observed effect is not restricted to one protocol or one form of decoder. It appears in processor instruction/control projections, communication command decoders, address filters, register controllers, USB request processing, and industrial communication protocols.
15.3 RQ3 — Pareto Alternatives
I²C, MDIO, USB CDC, USB HID, and several processor benchmarks exhibit distinct area-depth alternatives. DfS therefore appears naturally suited to multi-objective synthesis.
16. What the Results Do — and Do Not — Establish
Careful interpretation is important. The experiments demonstrate that the direct semantic synthesis approach can discover implementations that differ substantially from those obtained using the evaluated ABC flow.
They do not, by themselves, prove that conventional synthesis fundamentally cannot obtain such circuits. Nor do the experiments establish that a conventional tool necessarily discards all don't-care information. Such stronger claims would require a different experimental and theoretical analysis.
Direct synthesis under care-domain compatibility can discover implementations substantially different from—and, in these experiments, often smaller and shallower than—those obtained by the evaluated conventional synthesis flow.
17. Why Care-Domain Synthesis Can Produce Different Structures
For a PDBF, many globally defined circuits may satisfy the same semantic behavior on D while behaving differently outside D. Their circuit complexities may therefore differ. A structural optimization flow beginning from one representation explores transformations accessible from that representation under its chosen correctness and optimization mechanisms. Direct semantic synthesis instead searches under the constraint C|D=F.
This changes the search space. The experimental results suggest that, for some control functions, this difference can be substantial. We therefore view the care domain not merely as verification metadata but as a potentially useful synthesis resource.
18. Threats to Validity and Limitations
The benchmark set is dominated by combinational control logic, so the results should not automatically be generalized to arithmetic datapaths or arbitrary sequential circuits. ABC is the principal conventional synthesis reference, so the conclusions concern the evaluated reference flow rather than all possible conventional synthesis procedures.
Gates, levels, wires, and fan-out are technology-independent structural metrics. They are useful proxies but do not directly establish improvements in silicon area, timing, power, or energy.
Semantic benchmark construction must also be performed carefully. An omitted input assignment is a legitimate don't-care only when system semantics truly impose no requirement on its output. Finally, because synthesis operates on partial specifications, independent care-domain verification is essential.
19. Conclusion
This work investigated logic synthesis directly from partially defined semantic specifications. Instead of requiring a candidate implementation to reproduce one predetermined behavior over the complete Boolean input space, Design from Semantics requires compatibility only over the semantic care domain:
Behavior outside D remains unconstrained and can therefore participate in implementation optimization.
Experiments on processor-control projections and communication-protocol controllers demonstrate substantial structural differences between networks obtained by direct semantic synthesis and those obtained using the evaluated conventional ABC synthesis flow. The differences are observed not only in gate count but also in logic depth, wire count, and fan-out. Several benchmarks additionally expose useful Pareto trade-offs between area and depth.
For example, the verified SPI semantic controller decreases from 47 gates and 8 levels to 22 gates and 3 levels. The MDIO controller decreases from 31 gates and 7 levels to 17 gates and 4 levels, with an alternative 19-gate implementation reaching 3 levels. The USB HID example decreases from 242 gates and 20 levels to 36 gates and 6 levels, while a 42-gate alternative reaches four levels.
Direct synthesis under care-domain compatibility can discover implementations substantially different from—and, in these experiments, often smaller and shallower than—those obtained by the evaluated conventional synthesis flow.
We do not interpret this result as evidence that conventional synthesis is intrinsically incapable of exploiting don't-care information. Rather, it demonstrates that formulating synthesis directly in terms of semantic compatibility provides a distinct and experimentally productive implementation-search space.
Semantic incompleteness can itself be an optimization resource.