GT Synthesis

Examples

Three transparent paths into GT Synthesis

Each signature example isolates one central idea so that the reader can focus on PDBFs and Completion Optimization rather than application complexity.

01

Paper I

OR–XOR: one don’t-care, two implementations

The PDBF has one unspecified output. Completing it with 0 produces XOR; completing it with 1 produces OR. Both are legal, but OR is structurally simpler.

00 → 0
01 → 1
10 → 1
11 → X
The quality of the final circuit depends not only on logic optimization, but also on the selected completion.
02

Paper I

7SDD: explicit area–depth trade-offs

MethodAIG AND NodesLevels
Synopsys324
GT minimum depth184
GT balanced155
GT minimum nodes146
03

Paper III

Three-state controller: the sequential OR–XOR example

Three-state controller truth table
The two rows associated with unreachable state 11 are unspecified.

The controller has only two unreachable state/input combinations, yet GT finds a complete 3-output implementation with 4 gates, 2 levels, and 11 wires.

MethodGatesLevelsWires
ABC + deepsyn7317
ABC + transtoch6415
GT4211
Download PLADownload three PLAs
GT results for complete three-output controller
GT found 34 versions with the same measured optimum.